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9
Input event bus
3 2 1 0
AD0 conversion
completed
TIO8_udf
TIN0S
TID0_udf/ovf
CAN0_S0/S15
TIN3S
TID1_udf/ovf
CAN0_S1/S14
TID2_udf/ovf
TIN0S
AD1 conversion
completed
TIN19S
SIO0_TXD
TOU1_7irq
TIN20S
TOU0_0irq
TOU2_7irq
TOU0_1irq
SIO1_RXD
SIO3_TXD
TOU0_2irq
TOU0_6irq
TIN7S
AD1 conversion
completed
TOU0_7irq
3 2 1 0
Figure 9.1.1 Block Diagram of the DMAC
AD0 conversion
completed
TIO8_udf
S
S
Software
start
TIN13S
S
S
Software start
TIN18S
S
S
Software start
SIO0_TXD
SIO1_RXD
S
S
Software start
SIO0_RXD
S
S
Software start
S
S
SIO2_RXD
SIO1_TXD
TIN1S
S
S
Software start
SIO2_TXD
TIN2S
S
S
Software start
SIO3_RXD
Software start
S
S
SIO3_TXD
TIN8S
S
S
Software start
9-3
9.1 Outline of the DMAC
Output event bus
udf
DMA0
end
udf
DMA1
end
udf
DMA2
end
udf
DMA3
end
udf
DMA4
DMA0–4
end
interrupt
Software start
udf
DMA5
end
udf
DMA6
end
udf
DMA7
end
udf
DMA8
end
udf
DMA9
DMA5–9
end
interrupt
32180 Group User's Manual (Rev.1.0)
DMAC
0 1 2 3
0 1 2 3
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