Renesas M32R/ECU Series User Manual page 234

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Table 9.3.4 DMA Transfer Request Sources and Generation Timings on DMA3
REQSL3 DMA Transfer Request Source
0 0 Software start
0 1 Serial I/O0 (transmit buffer empty) When serial I/O0 transmit buffer is empty
1 0 Serial I/O1 (reception completed) When serial I/O1 reception is completed
1 1 Extended DMA3 transfer request
source selected
REQESEL3 DMA Transfer Request Source
0000 MJT (TIN0 input signal)
0001 One DMA2 transfer completed
0010 A-D1 conversion completed
0011 MJT (input event bus 1)
0100 MJT (input event bus 3)
0101 MJT (output event bus 2)
0110 MJT (output event bus 3)
0111 A-D0 conversion completed
1000 MJT (TIN0 input signal)
1001 MJT (TIO8_udf)
1010
| Settings inhibited
1111
Table 9.3.5 DMA Transfer Request Sources and Generation Timings on DMA4
REQSL4 DMA Transfer Request Source
0 0 Software start
0 1 One DMA3 transfer completed
1 0 Serial I/O0 (reception completed) When serial I/O0 reception is completed
1 1 Extended DMA4 transfer request
source selected
REQESEL4 DMA Transfer Request Source
0000 MJT (TIN19 input signal)
0001 Serial I/O0 (transmit buffer empty) When serial I/O0 transmit buffer is empty
0010 MJT (TOU1_7irq)
0011 MJT (input event bus 1)
0100 MJT (input event bus 3)
0101 MJT (output event bus 2)
0110 MJT (output event bus 3)
0111 A-D0 conversion completed
1000 MJT (TIN0 input signal)
1001 MJT (TIO8_udf)
1010
| Settings inhibited
1111
9.3 Functional Description of the DMAC
DMA Transfer Request Generation Timing
When any data is written to the DMA3 Software Request Generation Register
The source selected by the DMA3 Channel Control Register 1 (DM3CNT1)
REQESEL3 bits (see below)
DMA Transfer Request Generation Timing
When MJT TIN0 input signal is generated
When one DMA2 transfer is completed (cascade mode)
When A-D1 conversion is completed
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
–
DMA Transfer Request Generation Timing
When any data is written to the DMA4 Software Request Generation Register
When one DMA3 transfer is completed (cascade mode)
The source selected by the DMA4 Channel Control Register 1 (DM4CNT1)
REQESEL4 bits (see below)
DMA Transfer Request Generation Timing
When MJT TIN19 input signal is generated
MJT TOU1_7 interrupt source
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
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32180 Group User's Manual (Rev.1.0)
DMAC