Renesas M32R/ECU Series User Manual page 770

21
0.43VCC-BUS
BCLK
Address
(A11–A30)
CS#
(Access area)
CS#
(Non-access area)
RD#
Data input
(DB0–DB15)
BLW#
BHW#
Data output
(DB0–DB15)
WAIT#
Notes: • For signal-to-signal timing, see Figure 21.7.8, "Read Timing (Relative to Read Pulse),"
and Figure 21.7.9, "Write Timing (Relative to Write Pulse)."
• When using the threshold switching function, the data input and WAIT# voltage levels are
determined with respect to the rated minimum and maximum values for VIH and VIL.
Figure 21.7.6 Read and Write Timing (Relative to BCLK) with 1 or More Wait States
[16]
tc(BCLK)
[18]
tw(BCLKL)
[17]
tw(BCLKH)
[19]
td(BCLKH-A)
0.43VCC-BUS
0.16VCC-BUS
[20]
td(BCLKH-CS)
[20]
td(BCLKH-CS)
0.43VCC-BUS
[23] [92]
td(BCLKL-RDL)
0.16VCC-BUS
[25]
td(BCLKL-BLWL)
td(BCLKL-BHWL)
[29]
tpzx(BCLKL-DZ)
[27]
td(BCLKL-D)
[33]
tsu(WAITL-BCLKH)
0.16VCC-BUS
ELECTRICAL CHARACTERISTICS
21.7 A.C. Characteristics (when VCCE = 5 V)
0.16VCC-BUS
[21]
tv(BCLKH-A)
[22]
tv(BCLKH-CS)
0.43VCC-BUS
0.16VCC-BUS
[22]
tv(BCLKH-CS)
[24]
td(BCLKH-RDL) tv(BCLKH-RDL)
[31] [32]
tsu(D-BCLKH)
[97]
td(BCLKL-BLWH)
td(BCLKL-BHWH)
[26]
tv(BCLKL-BLWL)
tv(BCLKL-BHWL)
[28]
[30]
[34]
th(BCLKH-WAITL)
0.43VCC-BUS
[78] [79]
tsu(WAITH-BCLKH)
21-29
0.16VCC-BUS
0.43VCC-BUS
0.16VCC-BUS
th(BCLKH-D)
tv(BCLKH-D)
0.43VCC-BUS
0.16VCC-BUS
tpxz(BCLKH-DZ)
th(BCLKH-WAITH)
32180 Group User's Manual (Rev.1.0)