Sbi (System Break Interrupt) Control Register - Renesas M32R/ECU Series User Manual

5

5.2.3 SBI (System Break Interrupt) Control Register

SBI (System Break Interrupt) Control Register (SBICR)
b0 1 2
0 0 0
b Bit Name
0–6 No function assigned. Fix to "0"
7 SBIREQ
SBI request bit
Note 1: This bit can only be cleared (see below)
The System Break Interrupt (SBI) is an interrupt request generated by a falling edge on the SBI# signal input pin.
When a falling edge on the SBI# signal input pin is detected and this bit is set to "1", a system break interrupt
(SBI) request is generated to the CPU.
This bit cannot be set to "1" in software, it can only be cleared.
To clear this bit to "0", follow the procedure described below.
1. Write "1" to the SBI request bit.
2. Write "0" to the SBI request bit.
Note: • Unless this bit is set to "1", do not perform the above clearing operation.
3 4 5 6
SBIREQ
0 0 0 0
INTERRUPT CONTROLLER (ICU)
b7
0
Function
0: SBI not requested
1: SBI requested
5-7
5.2 ICU Related Registers
<Address: H'0080 0006>
<After reset: H'00>
R
0
R(Note 1)
32180 Group User's Manual (Rev.1.0)
W
0