Renesas M32R/ECU Series User Manual page 538

12
<UART on transmit side>
Transmit enable bit
Transmit buffer
empty bit
Transmit status bit
SIO transmit interrupt request
(Note 1)
(When transmit buffer empty
interrupt is selected)
(When transmission finished
interrupt is selected)
Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit
Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time)
Note 3: When transmission finished interrupt is enable
Note 4: The Interrupt Controller's IVECT register is read or the SIO Transmit Interrupt Control Register interrupt request bit cleared
Note 5: A transmit interrupt request is generated when transmission is enabled.
Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the
data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied.
Note 7: A transmission finished interrupt request is generated when data in the transmit shift register has all been transmitted.
Figure 12.6.6 Example of UART Transmission (Transmitted Successively)
<UART on transmit side>
TXD
Set
Write to the
transmit buffer
register
(First data)
ST
TXD
(Note 5)
(Note 2)
Interrupt request accepted (Note 4)
: Processing by software
12.6 Transmit Operation in UART Mode
<UART on receive side>
RXD
Write to the
transmit buffer
register
(Next data)
Transferred from the
transmit buffer to the
transmit shift register
(transmission starts)
First data
b7
b0 SP ST
Next data is written
upon transmit interrupt
(Note 2)(Note 6)
(Note 2)
(Note 3)
Interrupt request accepted (Note 4)
: Interrupt request generated
12-47
Cleared
Cleared when transfer of
the last data is completed
Next data
b7 b0 SP
(Note 3)(Note 7)
32180 Group User's Manual (Rev.1.0)
Serial I/O