Renesas M32R/ECU Series User Manual page 763

21
Symbol
td(CSL-RDL) Chip Select Delay Time before Read (
td(CSL-BLWL) Chip Select Delay Time before Write
td(CSL-BHWL)
td(CSL-WRL) Chip Select Delay Time before Write
(byte enable mode)
td(BCLKL-BLWH) Write Delay Time after BCLK
td(BCLKL-BHWH)
(6) Bus arbitration timing
Symbol
tsu(HREQL-BCLKH) HREQ# Input Setup Time before BCLK
th(BCLKH-HREQL) HREQ# Input Hold Time after BCLK
(7) Input transition time of JTAG pins
Symbol
tr High-going
Transition Time (JTCK, JTDI, JTMS, JTDO)
of Input
tf Low-going
Transition Time (JTCK, JTDI, JTMS, JTDO)
of Input
Note: • The rated values here are guaranteed for the case where the measured pin load capacitance CL = 80 pF.
21.7 A.C. Characteristics (when VCCE = 5 V)
Parameter
(
(
Parameter
Parameter
Other than JTRST pin
JTRST pin When using TAP
When not using TAP
Other than JTRST pin
JTRST pin When using TAP
When not using TAP
21-22
ELECTRICAL CHARACTERISTICS
Rated Value
MIN
tc(BCLK)
)×(1+S)-16
2
tc(BCLK)
)×(1+S)-15
2
tc(BCLK)
)×(1+S)-15
2
Rated Value
MIN
27
0
Rated Value
MIN
32180 Group User's Manual (Rev.1.0)
Unit See Figs.
21.7.6
21.7.8
MAX 21.7.9
21.7.10
ns [93]
ns [95]
ns [96]
14 ns [97]
Unit See Fig.
MAX 21.7.11
ns [35]
ns [36]
Unit See Fig.
MAX 21.7.12
10 ns [58]
10 ns
2 ms
10 ns [59]
10 ns
2 ms