Outline Of The Rtd Operation; Operation Of Rdr (Real-Time Ram Content Output) - Renesas M32R/ECU Series User Manual

Mitsubishi 32-bit risc single-chip microcomputers
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14
14.3 Functional Description of the RTD

14.3.1 Outline of the RTD Operation

Operation of the RTD is specified by a command entered from devices external to the chip. A command is
indicated by bits 16–19 (Note 1) of the RTD received data.
Table 14.3.1 RTD Commands
RTD Received Data
b19
b18
b17
b16
0
0
0
0
0
1
0
0
0
1
0
1
0
1
1
0
0
0
1
0
0
0
1
1
1
1
1
1
0
0
0
1
↑ (Note 1)
Note 1: The RTD received data bit 19 actually is not stored in the command register, and except for the RCV
command, handled as a "Don't care" bit. (Bits 16–18 are effective for the command specified.)
Note 2: The RCV command must always be transmitted twice in succession.
Note 3: For the RCV command, all bits, not just 16–19, (i.e., bits 0–15 and bits 20–31) must be set to "1".

14.3.2 Operation of RDR (Real-time RAM Content Output)

When the RDR (real-time RAM content output) command is issued, the RTD is enabled to transfer the contents
of the internal RAM to external devices without causing the CPU's internal bus to stop. Because the RTD reads
data from the internal RAM while there are no transfers performed between the CPU and internal RAM, no extra
CPU load is incurred.
Only the 32-bit word-aligned addresses can be specified for read from the internal RAM. (The two low-order
address bits specified by a command are ignored.) Data are read out and transferred from the internal RAM in
32-bit units.
RTDRXD
Note: • X = Don't care. (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.)
Figure 14.3.1 RDR Command Data Format
Command
Mnemonic
VER (VERify)
VEI (VErify Interrupt request)
RDR (ReaD RAM)
WRR (WRite RAM)
RCV (ReCoVer)
System reserved (use inhibited)
(LSB side)
31
20
19 18 17 16
X
X
0 0 1 0
Command (RDR)
REAL TIME DEBUGGER (RTD)
14.3 Functional Description of the RTD
RTD Function
Continuous monitor
RTD interrupt request
Real-time RAM content output
RAM content forcible rewrite (with verify)
Recover from runaway condition (Note 2), (Note 3)
(MSB side)
15
14 13 12
0
0
A29
A28
A17
Specified address
14-4
1
0
A16
32180 Group User's Manual (Rev.1.0)

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