Renesas M32R/ECU Series User Manual page 658

15
(6) Data bus (DB0–DB15)
This is the 16-bit bus used to access external devices. During external read access, data is latched from the
bus synchronously with the rising edge of the read strobe. Even during 8-bit read, 16-bit data is always read
in, but data only on the valid byte position is transferred into the internal circuit. During external write access,
data is output from the bus. During 8-bit write, the valid byte position to write is indicated by the output signal
BHW# or BLW#. When accessing the internal area, the bus functions as an input bus.
Note: • During external extension mode, these pins are switched for port after reset. Their pin functions must
be set for data bus using the corresponding Port Operation Mode Register as necessary.
(7) System clock/write (BCLK/WR#)
The pin function changes depending on the Bus Mode Control Register (BUSMODC).
When BUSMOD = "0" and this signal is System Clock (BCLK), it outputs the system clock necessary to
synchronize operations in an external system. When the CPU clock = 80 MHz, a 20 MHz clock is output from
BCLK. When not using the BCLK/WR function, this pin can be used as P70 by clearing the P7 Operation
Mode Register P70MD bit to "0".
When BUSMOD = "1" and this signal is Write (WR#), during external write access it indicates the valid data
transferred on the data bus. During external read cycle and when accessing the internal area it outputs a high.
Note: • During external extension mode, this pin is switched for port after reset. Its pin function must be set
for system clock/write using the corresponding Port Operation Mode Register as necessary.
(8) Wait (WAIT#)
When the 32180 started an external bus cycle, it automatically inserts wait states while the WAIT# input
signal is asserted. For details, see Chapter 16, "Wait Controller." When not using the WAIT function, this pin
can be used as P71 by clearing the P7 Operation Mode Register P71MD bit to "0".
Note: • During external extension mode, this pin is switched for port after reset. Its pin function must be
set for wait using the corresponding Port Operation Mode Register as necessary.
(9) Hold control (HREQ#, HACK#)
The hold state refers to a state in which the microcomputer has stopped accessing the bus and the bus
interface related pins are tristated (high impedance). While the microcomputer is in a hold state, any bus
master external to the chip can use the system bus to transfer data.
A low signal input on the HREQ# pin places the microcomputer into a hold state. While the microcomputer
remains in a hold state after accepting the hold request and during a transition to the hold state, the HACK#
pin outputs a low-level signal. To exit the hold state and return to normal operating state, release the HREQ#
signal back high.
Note: • During external extension mode, these pins are switched for port after reset. Their pin functions must
be set for hold control using the corresponding Port Operation Mode Register as necessary.
The status of each pin during hold are shown below.
Table 15.1.1 Pin State during Hold Period
Pin Name
A11–A30, DB0–DB15, CS0#–CS3#, RD#, BHW#, BLW#, BHE#, BLE#, WR#
HACK#
Other pins (e.g., ports and timer output)
(10) Bus power supply (VCC-BUS)
This pin supplies power to the bus control pins. A voltage different from that of the main power supply can be
applied, which is convenient when external devices are connected to the system.
EXTERNAL BUS INTERFACE
15.1 Outline of the External Bus Interface
15-3
Pin State or Operation
High impedance
Output a low
Normal operation
32180 Group User's Manual (Rev.1.0)