Renesas M32R/ECU Series User Manual page 692

16
Bus Mode Control Register (Note 1)
BUSMOD bit = 0 (WR signal separated)
CS Area Wait Control Register (Note 2)
WTCSEL bit = 001 (1 wait)
SWAIT bit = 0 (without strobe wait)
RECOV bit = 1 (with recovery cycle)
IDLE bit = 1 (with idle cycle)
Read
CS0#–CS3#
BHW#, BLW#
DB0–DB15
Write
CS0#–CS3#
BHW#, BLW#
DB0–DB15
Note 1: For details about the Bus Mode Control Register, see Section 15.2.3, "Bus Mode Control Register."
Note 2: For details about the CS Area Wait Control Register, see Section 16.2.1, "CS Area Wait Control Registers."
Notes: • Circles in the above diagram indicate the sampling timing.
• No idle cycles are added after the write cycle.
Figure 16.3.10 Read/Write Timing (Internal 2 Wait States + Recovery and Idle Cycles Added)
BCLK
A11–A30
RD#
"H"
WAIT#
(Don't Care)
BCLK
A11–A30
RD#
"H"
WAIT#
(Don't Care)
16.3 Typical Operation of the Wait Controller
Read (4 cycles)
Internal Recovery Idle
1 wait state cycle cycle
(Don't Care)
"H"
Write (3 cycles)
Internal Recovery
1 wait state cycle
(Don't Care)
"H"
16-15
WAIT CONTROLLER
32180 Group User's Manual (Rev.1.0)