Renesas M32R/ECU Series User Manual page 814

Appendix 4
Appendix 4.8.3 Precautions on Using TOP Continuous Output Mode
The following describes precautions to be observed when using TOP continuous output mode.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
• If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter
value temporarily reads as H'FFFF but immediately changes to (reload value – 1) at the next clock edge.
• Because the timer operates synchronously with the count clock, a count clock-dependent delay is included
before F/F output is inverted after the timer is enabled.
Appendix 4.8.4 Precautions on Using TIO Measure Free-Run/Clear Input Modes
The following describes precautions to be observed when using TIO measure free-run/clear input modes.
• If measure event input and write to the counter occur in the same clock period, the write value is set in the
counter while at the same time latched into the measure register.
Appendix 4.8.5 Precautions on Using TIO PWM Output Mode
The following describes precautions to be observed when using TIO PWM output mode.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
• If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter
value temporarily reads as H'FFFF but immediately changes to (reload value – 1) at the next clock edge.
• Because the timer operates synchronously with the count clock, a count clock-dependent delay is included
before F/F output is inverted after the timer is enabled.
Appendix 4.8.6 Precautions on Using TIO Single-Shot Output Mode
The following describes precautions to be observed when using TIO single-shot output mode.
• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,
the former has priority so that the counter stops.
• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable
bit, the latter has priority so that count is enabled.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable
bit, the latter has priority so that count is disabled.
• Because the timer operates synchronously with the count clock, a count clock-dependent delay is included
before F/F output is inverted after the timer is enabled.
Appendix 4.8 Precautions about the Multijunction Timers
Appendix 4-9
SUMMARY OF PRECAUTIONS
32180 Group User's Manual (Rev. 1.0)