Renesas M32R/ECU Series User Manual page 235

9
Table 9.3.6 DMA Transfer Request Sources and Generation Timings on DMA5
REQSL5 DMA Transfer Request Source
0 0 Software start or one DMA7
transfer completed
0 1 All DMA0 transfers completed
1 0 Serial I/O2 (reception completed) When serial I/O2 reception is completed
1 1 Extended DMA5 transfer request
source selected
REQESEL5 DMA Transfer Request Source
0000 MJT (TIN20 input signal)
0001 MJT (TOU0_0irq)
0010 MJT (TOU2_7irq)
0011 MJT (input event bus 1)
0100 MJT (input event bus 3)
0101 MJT (output event bus 2)
0110 MJT (output event bus 3)
0111 A-D0 conversion completed
1000 MJT (TIN0 input signal)
1001 MJT (TIO8_udf)
1010
| Settings inhibited
1111
Table 9.3.7 DMA Transfer Request Sources and Generation Timings on DMA6
REQSL6 DMA Transfer Request Source
0 0 Software start
0 1 Serial I/O1 (transmit buffer empty) When serial I/O1 transmit buffer is empty
1 0 MJT (TIN1 input signal)
1 1 Extended DMA6 transfer request
source selected
REQESEL6 DMA Transfer Request Source
0000 One DMA5 transfer completed
0001 MJT (TOU0_1irq)
0010 Serial I/O1 (reception completed) When serial I/O1 reception is completed
0011 MJT (input event bus 1)
0100 MJT (input event bus 3)
0101 MJT (output event bus 2)
0110 MJT (output event bus 3)
0111 A-D0 conversion completed
1000 MJT (TIN0 input signal)
1001 MJT (TIO8_udf)
1010
| Settings inhibited
1111
9.3 Functional Description of the DMAC
DMA Transfer Request Generation Timing
When any data is written to the DMA5 Software Request Generation Register
(software start) or when one DMA7 transfer is completed (cascade mode)
When all DMA0 transfers are completed (cascade mode)
The source selected by the DMA5 Channel Control Register 1 (DM5CNT1)
REQESEL5 bits (see below)
DMA Transfer Request Generation Timing
When MJT TIN20 input signal is generated
MJT TOU0_0 interrupt source
MJT TOU2_7 interrupt source
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
–
DMA Transfer Request Generation Timing
When any data is written to the DMA4 Software Request Generation Register
When MJT TIN1 input signal is generated
The source selected by the DMA6 Channel Control Register 1 (DM6CNT1)
REQESEL6 bits (see below)
DMA Transfer Request Generation Timing
When one DMA5 transfer is completed (cascade mode)
MJT TOU0_1 interrupt source
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
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32180 Group User's Manual (Rev.1.0)
DMAC