Renesas M32R/ECU Series User Manual page 405

10
The TOU counters operate as a 24-bit down-counter when in single-shot output, delayed single-shot output or
continuous output mode. After the timer is enabled (by writing to the enable bit in software or upon occurrence of
the event selected by the TOU enable source select bit), the counter starts counting synchronously with the
count clock. Bits 8–15 and bits 16–31 are the 8 high-order and the 16 low-order bits of the counter, respectively.
Bits 0–7 are ignored.
When writing to the counter separately in high and low-order bits, rewrite the 8 high-order bits first and then the
16 low-order bits. The 8 high-order bits become effective when the 16 low-order bits are rewritten. If the counter
is rewritten in the reverse order beginning with the 16 low-order bits, the value of the 8 high-order bits is not
reflected until the next time the 16 low-order bits are rewritten. If the 8 high-order bits are read before the CPU
has finished rewriting the 16 low-order bits after rewriting the 8 high-order bits. The read value shows the
previous data (when not counting) or the current count of the previous data (when count is in progress), and not
the new rewritten data. If the counter is written to in 32-bit units, it is rewritten successively in order of the 8 high-
order bits and then the 16 low-order bits automatically.
During PWM output or single-shot PWM output mode, the TOU counters operate as a 16-bit down-counter
where only the 16 low-order bits are effective. For details, see Section 10.8.5, Paragraph (2), "TOU counters
during PWM output and single-shot PWM output modes."
To read the counter on-the-fly, make sure the read timing does not coincide with an underflow of the 16 low-
order bits (8 high-order bits decremented). When reading the counter on-the-fly, take the appropriate measure
to ensure that the read value is correct by, for example, reading the counter twice in succession.
Count clock
Counter value
Upper counter read
Lower counter read
Read value (first time)
Read value (second time)
Note 1: If the counter underflows, the 8 high-order bits become 'FF' and the read value cannot be
guaranteed to be correct. Check the count enable bit to see if count is in progress as necessary.
Notes: • In cases where the count clock is significantly fast compared with the read interval, read also
the lower counter twice as necessary.
• If interrupt processing, etc. occurs while reading the counter, the read value cannot be guaranteed
to be correct. Therefore, disable interrupts during read.
Figure 10.8.3 Example of How to Read the Counter Value
FF 0000 FE FFFF
FF FFFF
FE FFFF
10-162
MULTIJUNCTION TIMERS
10.8 TOU (Output-Related 24-Bit Timer)
FE FFFE
Read value is incorrect
Smaller of the two (Note 1)
Correct value
32180 Group User's Manual (Rev.1.0)