Renesas M32R/ECU Series User Manual page 220

9
DMA9 Channel Control Register 0 (DM9CNT0)
b0 1 2
MDSEL9 TREQF9 REQSL9
0 0 0
b Bit Name
0 MDSEL9
DMA9 transfer mode select bit
1 TREQF9
DMA9 transfer request flag bit
2, 3 REQSL9
DMA9 transfer request source select bit
4 TENL9
DMA9 transfer enable bit
5 TSZSL9
DMA9 transfer size select bit
6 SADSL9
DMA9 source address direction select bit
7 DADSL9
DMA9 destination address direction select bit
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA9 Channel Control Register 1 (DM9CNT1)
b8 9 10
0 0 0
b Bit Name
8–11 No function assigned. Fix to "0".
12–15 REQESEL9
Extended DMA9 transfer request source select bit
3 4 5 6
TENL9 TSZSL9 SADSL9 DADSL9
0 0 0 0
11 12 13 14
REQESEL9
0 0 0 0
b7
0
Function
0: Normal mode
1: Ring buffer mode
0: Transfer not requested
1: Transfer requested
00: Software start
01: SIO3_TXD (transmit buffer empty)
10: MJT(TIN8S)
11: Extended DMA9 transfer request source select
(DMA9 Channel Control Register 1)
0: Disable transfer
1: Enable transfer
0: 16 bits
1: 8 bits
0: Fixed
1: Increment
0: Fixed
1: Increment
b15
0
Function
0000: One DMA8 transfer completed
0001: MJT(TOU0_7irq)
0010: AD1 conversion completed
0011: Common 1) MJT (input event bus 1)
0100: Common 2) MJT (input event bus 3)
0101: Common 3) MJT (output event bus 2)
0110: Common 4) MJT (output event bus 3)
0111: Common 5) AD0 conversion completed
1000: Common 6) MJT (TIN0S)
1001: Common 7) MJT (TIO8_udf)
1010: Settings inhibited
| |
1111: Settings inhibited
9-15
9.2 DMAC Related Registers
<Address: H'0080 0458>
<After reset: H'00>
<Address: H'0080 0459>
<After reset: H'00>
32180 Group User's Manual (Rev.1.0)
DMAC
R W
R W
R(Note 1)
R W
R W
R W
R W
R W
R W
0 0
R W