Renesas M32R/ECU Series User Manual page 812

Appendix 4
correction register
Reload register
Correction register
TOP interrupt request
due to underflow
Figure 4.8.1 Example of an Operation in TOP Single-shot Output Mode Where Count Overflows Due to Correction
Appendix 4.8 Precautions about the Multijunction Timers
Enabled
(by writing to the enable bit
or by external input)
Count clock
Enable bit
Write to the
H'FFFF
H'FFF8
Indeterminate
value
Counter
H'0000
H'FFF8
Indeterminate
F/F output
Data inverted
Note: • This diagram does not show detailed timing information.
SUMMARY OF PRECAUTIONS
Disabled
(by underflow)
Overflow occurs
H'(FFF0+0014)
H'FFFF
H'(FFF8-1)
H'FFF0
H'0004
Actual count after overflow
H'0014
Data inverted
by enable by underflow
Appendix 4-7
32180 Group User's Manual (Rev. 1.0)