Renesas M32R/ECU Series User Manual page 436

10
(by writing to the enable bit or by
Count clock
Enable bit
Counter
Reload 0 register
Reload 1 register
F/F output
Interrupt request
due to underflow
Note 1: DMA transfer request also is generated with the same timing.
Note: • This diagram does not show detailed timing information.
Figure 10.8.17 Typical Operation in PWM Output Mode (Reload 0 Register: H'FFFF)
Enabled
Superficial
external input)
underflow
Count down from
register set value
H'FFFF
Undefined
value
H'E000
H'0000
H'FFFF
H'E000
Data not inverted
(Note 1)
• This diagram is shown with respect to the one-count-clock delayed output.
10.8 TOU (Output-Related 24-Bit Timer)
Because the reload 0 register = H'FFFF,
a superficial underflow is generated,
causing the counter to be loaded with
the content of the reload 1 register
Underflow
Count down from
the reload 1
the reload 1
register set value
H'(FFFF-1) H'(FFFF-1)
H'(E000-1)
Data not inverted
Timing at which startup requests to other timers are generated
10-193
MULTIJUNCTION TIMERS
H'(E000-1)
Data not inverted
32180 Group User's Manual (Rev.1.0)