Renesas M32R/ECU Series User Manual page 228

9
Example for clearing interrupt request status
Write to the interrupt request status
b4 5 6
1 1 0
Program example
• To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit)
To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time,
avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation
and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared.
Event occurs on bit 6
Event occurs on bit 4
Figure 9.2.3 Example for Clearing Interrupt Request Status
Initial state
Event occurs on bit 6
Event occurs on bit 4
b7
1
ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */
ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */
Interrupt request status
b4 5
0 0
1 0
0 0
9.2 DMAC Related Registers
Interrupt request status
b4 5 6 b7
0 0 0 0
0 0 1 0
1 0 1 0
1 0 0 0
6 b7
1 0
Read
0 0 1
1 0
0 0 0
Write
0 0
Only bit 6 cleared
Bit 4 also cleared
9-23
Interrupt request
Only bit 6 cleared
Bit 4 data retained
0
Clear bit 6 (AND'ing with 1101)
0
32180 Group User's Manual (Rev.1.0)
DMAC