Renesas M32R/ECU Series User Manual page 771

21
BCLK
Address
(A11–A30)
CS0#, CS1#,
CS2#, CS3#
RD#
Data input
(DB0–DB15)
BLW#
BHW#
Data output
(DB0–DB15)
Note: • When using the threshold switching function, the data input voltage levels are determined
with respect to the rated minimum and maximum values for VIH and VIL.
Figure 21.7.7 Read and Write Timing (Relative to BCLK) with Zero Wait State
[16]
tc(BCLK)
[18]
tw(BCLKL)
0.43VCC-BUS
[17]
tw(BCLKH)
[20]
td(BCLKH-CS)
[19]
td(BCLKH-A)
0.43VCC-BUS
0.16VCC-BUS
[23]
td(BCLKL-RDL)
[31]
tsu(D-BCLKH)
[25]
td(BCLKL-BLWL)
td(BCLKL-BHWL)
[29]
tpzx(BCLKL-DZ)
[27]
ELECTRICAL CHARACTERISTICS
21.7 A.C. Characteristics (when VCCE = 5 V)
0.16VCC-BUS
[22]
tv(BCLKH-CS)
[21]
tv(BCLKH-A)
[24]
tv(BCLKH-RDL)
0.16VCC-BUS
0.43VCC-BUS
0.16VCC-BUS
[32]
th(BCLKH-D)
0.16VCC-BUS
[90]
tv(BCLKH-BLWL)
tv(BCLKH-BHWL)
[28]
tv(BCLKH-D)
0.43VCC-BUS
0.16VCC-BUS
[30]
tpxz(BCLKH-DZ)
td(BCLKL-D)
21-30
32180 Group User's Manual (Rev.1.0)