Floating-Point Status Register: Fpsr (Cr7) - Renesas M32R/ECU Series User Manual

2

2.3.5 Floating-point Status Register: FPSR (CR7)

b0 1 2
FS FX FU
0 0 0
b16 17 18
EX EU
0 0 0
b Bit Name
0 FS
Floating-point Exception Summary Bit
1 FX
Inexact Exception Flag
2 FU
Underflow Exception Flag
3 FZ
Zero Divide Exception Flag
4 FO
Overflow Exception Flag
5 FV
Invalid Operation Exception Flag
6–16 No function assigned. Fix to "0".
17 EX
Inexact Exception Enable Bit
18 EU
Underflow Exception Enable Bit
19 EZ
Zero Divide Exception Enable Bit
20 EO
Overflow Exception Enable Bit
21 EV
Invalid Operation Exception Enable Bit
22 No function assigned. Fix to "0".
23 DN
Denormalized Number Zero Flush Bit
(Note 2)
24 CE
Unimplemented Operation
Exception Cause Bit
25 CX
Inexact Exception Cause Bit
3 4 5 6 7
FZ FO FV
0 0 0 0 0
19 20 21 22 23
EZ EO EV DN
0 0 0 0 1
Function
Reflects the logical sum of FU, FZ, FO and FV.
Set to "1" when an inexact exception occurs (if EIT processing is
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
Set to "1" when an underflow exception occurs (if EIT processing is
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
Set to "1" when a zero divide exception occurs (if EIT processing is
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
Set to "1" when an overflow exception occurs (if EIT processing is
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
Set to "1" when an invalid operation exception occurs (if EIT processing
is unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
0: Mask EIT processing to be executed when an inexact exception occurs.
1: Execute EIT processing when an inexact exception occurs.
0: Mask EIT processing to be executed when an underflow exception
occurs.
1: Execute EIT processing when an underflow exception occurs.
0: Mask EIT processing to be executed when a zero divide exception
occurs.
1: Execute EIT processing when a zero divide exception occurs.
0: Mask EIT processing to be executed when an overflow exception
occurs.
1: Execute EIT processing when an overflow exception occurs.
0: Mask EIT processing to be executed when an invalid operation
exception occurs.
1: Execute EIT processing when an invalid operation exception occurs.
0: Handle the denormalized number as a denormalized number.
1: Handle the denormalized number as zero.
0: No unimplemented operation exception occurred.
1: An unimplemented operation exception occurred. When the bit is
set to "1", the execution of an FPU operation instruction will clear it to "0".
0: No inexact exception occurred.
1: An inexact exception occurred. When the bit is set to "1",
the execution of an FPU operation instruction will clear it to "0".
8 9 10 11 12
0 0 0 0 0
24 25 26 27 28
CE CX CU CZ CO
0 0 0 0 0
2-5
2.3 Control Registers
13 14 b15
0 0 0
29 30 b31
CV RM
0 0 0
<After reset: H'0000 0100>
R
R
R
R
R
R
R
0
R
R
R
R
R
0
R
R
R
32180 Group User's Manual (Rev.1.0)
CPU
W
–
W
W
W
W
W
0
W
W
W
W
W
0
W
(Note 3)
(Note 3)