Renesas M32R/ECU Series User Manual page 114

5
SBI#
Peripheral circuits
Interrupt request
Interrupt request
Interrupt request
Interrupt
control circuit
Interrupt
control circuit
Interrupt
control circuit
Figure 5.1.1 Block Diagram of the Interrupt Controller
System Break Interrupt (SBI)
SBI Control Register
Edge
IREQ
Edge
IREQ
Edge
IREQ
IREQ
Level
IREQ
Level
IREQ
Level
INTERRUPT CONTROLLER (ICU)
5.1 Outline of the Interrupt Controller
Interrupt Controller
request generated
(nonmaskable)
SBIREQ
(SBICR)
External Interrupt (EI)
ILEVEL
request generated
(maskable)
Interrupt Vector Register
IMASK
compari-
son
NEW_IMASK
Interrupt Request Mask
Register (IMASK)
Interrupt Control Register
5-3
SBI
To the CPU core
(IVECT)
EI
To the CPU core
32180 Group User's Manual (Rev.1.0)