Block Diagram - Renesas M32R/ECU Series User Manual

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1.2 Block Diagram

Figure 1.2.1 shows a block diagram of the 32180. The features of each block are described in Table 1.2.1.
M32R-FPU Core
(80 MHz)
Multiplier/Accumulator
(32 bits × 16 bits + 56 bits)
Single-precision FPU
(fully IEEE 754 compliant)
Internal Flash Memory
(1 Mbytes = 1,024 Kbytes)
Internal RAM
(48 Kbytes)
Real-Time Debugger
(RTD)
PLL Clock Generator
Internal Power Supply
Generator (VDC)
Figure 1.2.1 Block Diagram of the 32180
Internal Bus
Interface
(10 channels)
Multijunction Timer
(64 channels)
A-D Converter × 2
(A-D0 : 10-bit converter, 16 channels)
(A-D1 : 10-bit converter, 16 channels)
Interrupt Controller
(32 sources, 8 levels)
Wait Controller
External Bus
Interface
Data Address
Input/output ports, 158 lines
1-5
OVERVIEW
1.2 Block Diagram
DMAC
Serial I/O
(6 channels)
Full CAN
(2 channels)
32180 Group User's Manual (Rev.1.0)