Comparator Operation - Renesas M32R/ECU Series User Manual

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The conversion result is stored in the 10-bit A-D Data Register (AD0DTn, AD1DTn) corresponding to each
converted channel. There is also an 8-bit A-D Data Register (AD08DTn, AD18DTn) for each channel, from
which the 8 high-order bits of the 10-bit conversion result can be read out.
The following shows the procedure for A-D conversion by a successive approximation method in each operation mode.
(1) Single mode
The convert operation stops when comparison for the A-D Successive Approximation Register bit 15 is
completed. The content (A-D conversion result) of the A-D Successive Approximation Register is transferred
to the 10-bit A-D Data Registers 0–15 for the converted channel.
(2) Single-shot scan mode
When comparison for the A-D Successive Approximation Register bit 15 on a specified channel is completed, the
content of the A-D Successive Approximation Register is transferred to the corresponding 10-bit A-D Data Regis-
ters 0–15, and the convert operations in steps 2 to 7 above are reexecuted for the next channel to be converted.
In single-shot scan mode, the convert operation stops when A-D conversion in one specified scan loop is completed.
(3) Continuous scan mode
When comparison for the A-D Successive Approximation Register bit 15 on a specified channel is completed, the
content of the A-D Successive Approximation Register is transferred to the corresponding 10-bit A-D Data Regis-
ters 0–15, and the convert operations in steps 2 to 7 above are reexecuted for the next channel to be converted.
In continuous scan mode, the convert operation is executed continuously until scan operation is forcibly termi-
nated by setting the A-D conversion stop bit (Scan Mode Register 0 bit 6) to "1".

11.3.3 Comparator Operation

When comparator mode (single mode only) is selected, the A-D Converter functions as a comparator which
compares analog input voltages with the comparison voltage that is set by software.
When a comparison value is written to the successive approximation register, the A-D Converter starts
"comparating" the analog input voltage selected by the Single Mode Register 1 analog input select bit with the
value written into the successive approximation register. Once comparate begins, the following operation is
automatically executed.
1. The A-D Single Mode Register 0 or A-D Scan Mode Register 0 A-D conversion/comparate completion bit
is cleared to "0".
2. The comparison voltage, Vref (Note 1), is fed from the D-A Converter into the comparator.
3. The comparison voltage, Vref, and the analog input voltage, VIN, are compared, with the comparison
result stored in the comparate result flag for the corresponding channel.
If Vref < VIN, then the comparate result flag = 0
If Vref > VIN, then the comparate result flag = 1
4. The comparate operation is stopped after storing the comparison result.
The comparison result is stored in the A-D Comparate Data Register (AD0CMP, AD1CMP)'s corresponding bit.
Note 1: The comparison voltage, Vref (the voltage fed from the D-A Converter into the comparator), is
determined according to changes of the A-D Successive Approximation Register content. Shown
below are the equations used to calculate the comparison voltage, Vref.
• If the A-D Successive Approximation Register content = 0
• If the A-D Successive Approximation Register content = 1 to 1,023
Vref [V] = 0
Vref [V] = (reference voltage VREF / 1,024) x (A-D Successive Approximation Register content – 0.5)
11.3 Functional Description of A-D Converters
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A-D Converters
32180 Group User's Manual (Rev.1.0)