Dma Transfer Processing Procedure - Renesas M32R/ECU Series User Manual

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9.3.2 DMA Transfer Processing Procedure

Shown below is an example of how to control DMA transfer in cases when performing transfer on DMA channel 0.
Setting interrupt
controller-related
registers
Setting
DMAC-related
registers
Starting DMA transfer
DMA transfer
completed
Figure 9.3.1 Example of a DMA Transfer Processing Procedure
DMA transfer
processing starts
Set the interrupt controller's
DMA0-4 Interrupt Control Register
Set DMA0 Channel Control Register 0
Set DMA0-4 Interrupt Request Status Registers 0 and 1
Set DMA0-4 Interrupt Request Mask Register
Set DMA0 Source Address Register
Set DMA0 Destination Address Register
Set DMA0 Count Register
Set DMA0 Channel Control Registers 0 and 1
DMA transfer starts as requested by
internal peripheral I/O
Transfer count register underflows
Interrupt request generated
DMA operation
completed
9-33
9.3 Functional Description of the DMAC
• Interrupt priority level
• Transfers disabled
• Interrupt request status
bits cleared
• Interrupt request enabled
• Source address of transfer
• Destination address of transfer
• Number of times DMA transfer
is performed
• Transfer mode, request source,
transfer size, address direction
and transfer enable
32180 Group User's Manual (Rev.1.0)
DMAC