Renesas M32R/ECU Series User Manual page 667

15
Bus Mode Control Register (Note 1)
BUSMOD bit = 0 (WR signal separated)
CS Area Wait Control Register (Note 2)
WTCSEL bit = 010 (2 wait)
SWAIT bit = 0 (without strobe wait)
RECOV bit = 0 (without recovery cycle)
IDLE bit = 0 (without idle cycle)
Read
BHW#, BLW#
Write
CS0#–CS3#
BHW#, BLW#
Note 1: For details about the Bus Mode Control Register, see Section 15.2.3, "Bus Mode Control Register."
Note 2: For details about the CS Area Wait Control Register, see Section 16.2.1, "CS Area Wait Control Registers."
Note: • Circles in the above diagram denote the sampling timing.
Figure 15.3.3 Read/Write Timing (for Access with Internal 2 and External 1 Wait States)
BCLK
A11–A30
CS0#–CS3#
RD#
"H"
DB0–DB15
WAIT#
(Don't Care)
BCLK
A11–A30
RD#
"H"
DB0–DB15
WAIT#
(Don't Care)
EXTERNAL BUS INTERFACE
Read (4 cycles)
External
Internal
1 wait state
2 wait states
(Don't Care)
"H"
"L"
Write (4 cycles)
External
Internal
1 wait state
2 wait states
(Don't Care)
"H"
"L"
15-12
15.3 Read/Write Operations
32180 Group User's Manual (Rev.1.0)