Renesas M32R/ECU Series User Manual page 61

Mitsubishi 32-bit risc single-chip microcomputers
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3
SFR Area Register Map (3/27)
Address
b0
H'0080 0116
SIO0 Receive Control Register
|
H'0080 0120
SIO1 Transmit Control Register
H'0080 0122
H'0080 0124
H'0080 0126
SIO1 Receive Control Register
|
H'0080 0130
SIO2 Transmit Control Register
H'0080 0132
H'0080 0134
H'0080 0136
SIO2 Receive Control Register
|
H'0080 0140
SIO3 Transmit Control Register
H'0080 0142
H'0080 0144
H'0080 0146
SIO3 Receive Control Register
|
H'0080 0180
CS0 Area Wait Control Register
H'0080 0182
CS2 Area Wait Control Register
|
H'0080 01E0
H'0080 01E2
H'0080 01E4
H'0080 01E6
H'0080 01E8
H'0080 01EA
H'0080 01EC
H'0080 01EE
H'0080 01F0
H'0080 01F2
H'0080 01F4
H'0080 01F6
|
H'0080 0200
H'0080 0202
+0 address
(S0RCNT)
(S1TCNT)
SIO1 Transmit Buffer Register
SIO1 Receive Buffer Register
(S1RCNT)
(S2TCNT)
SIO2 Transmit Buffer Register
SIO2 Receive Buffer Register
(S2RCNT)
(S3TCNT)
SIO3 Transmit Buffer Register
SSIO3 Receive Buffer Register
(S3RCNT)
(CS0WTCR)
(CS2WTCR)
Flash Mode Register
(FMOD)
Flash Control Register 1
(FCNT1)
Flash Control Register 3
(FCNT3)
Virtual Flash S Bank Register 0
Virtual Flash S Bank Register 1
Virtual Flash S Bank Register 2
Virtual Flash S Bank Register 3
Virtual Flash S Bank Register 4
Virtual Flash S Bank Register 5
Virtual Flash S Bank Register 6
Virtual Flash S Bank Register 7
(Use inhibited area)
Prescaler Register 0
(PRS0)
3.4 Internal RAM and SFR Areas
b7 b8
SIO0 Baud Rate Register
(Use inhibited area)
SIO1 Transmit/Receive Mode Register
(S1TXB)
(S1RXB)
SIO1 Baud Rate Register
(Use inhibited area)
SIO2 Transmit/Receive Mode Register
(S2TXB)
(S2RXB)
SIO2 Baud Rate Register
(Use inhibited area)
SIO3 Transmit/Receive Mode Register
(S3TXB)
(S3RXB)
SIO3 Baud Rate Register
(Use inhibited area)
CS1 Area Wait Control Register
CS3 Area Wait Control Register
(Use inhibited area)
Flash Status Register 1
Flash Control Register 2
Flash Control Register 4
(Use inhibited area)
(FESBANK0)
(FESBANK1)
(FESBANK2)
(FESBANK3)
(FESBANK4)
(FESBANK5)
(FESBANK6)
(FESBANK7)
(Use inhibited area)
Clock Bus & Input Event Bus Control Register
Prescaler Register 1
3-10
ADDRESS SPACE
+1 address
(S0BAUR)
(S1MOD)
(S1BAUR)
(S2MOD)
(S2BAUR)
(S3MOD)
(S3BAUR)
(CS1WTCR)
(CS3WTCR)
(FSTAT1)
(FCNT2)
(FCNT4)
(CKIEBCR)
(PRS1)
32180 Group User's Manual (Rev.1.0)
See pages
b15
12-20
12-23
12-14
12-15
12-18
12-19
12-20
12-23
12-14
12-15
12-18
12-19
12-20
12-23
12-14
12-15
12-18
12-19
12-20
12-23
16-4
16-4
6-4
6-5
6-7
6-8
6-9
6-11
6-11
6-11
6-11
6-11
6-11
6-11
6-11
10-16
10-12

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