Renesas M32R/ECU Series User Manual page 513

12
(6) FLM (Framing Error) bit (Bit 6)
This bit is effective in only UART mode. It is fixed to "0" during CSIO mode.
[Set condition]
The FLM (Framing Error) bit is set to "1" when the number of received bits does not agree with one that
was set by the SIO Transmit/Receive Mode Register.
[Clear condition]
The FLM bit is cleared to "0" by reading out the lower byte of the SIO Receive Buffer Register or by
clearing the SIO Receive Control Register REN (Receive Enable) bit.
However, if an overrun error occurs, this bit cannot be cleared by reading out the lower byte of the
Receive Buffer Register. In this case, clear the REN (Receive Enable) bit.
(7) ERS (Error Sum) bit (Bit 7)
[Set condition]
This flag is set to "1" when any one of overrun, framing or parity errors is detected at completion of
reception.
[Clear condition]
If the detected error was an overrun error, this flag is cleared by clearing the REN (Receive Enable) bit
to "0". Otherwise, this flag is cleared by reading out the lower byte of the SIO Receive Buffer Register or
by clearing the SIO Receive Control Register REN (Receive Enable) bit.
12.2 Serial I/O Related Registers
12-22
Serial I/O
32180 Group User's Manual (Rev.1.0)