Renesas M32R/ECU Series User Manual page 121

5
Interrupt request from
each internal peripheral I/O
Bit 3 or 11
Data bus
Figure 5.2.1 Configuration of the Interrupt Control Register (Edge-recognized Type)
Interrupt request from each
group internal peripheral I/O
Data bus
Figure 5.2.2 Configuration of the Interrupt Control Register (Level-recognized Type)
(2) ILEVEL (Interrupt Priority Level) (Bits 5–7 or bits 13–15)
These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set these bits to '111'
to disable or any value '000' through '110' to enable the interrupt from some internal peripheral I/O.
When an interrupt occurs, the Interrupt Controller resolves priority between this interrupt and other interrupt
sources based on ILEVEL settings and finally compares priority with the IMASK value to determine whether
to forward an EI request to the CPU or keep the interrupt request pending.
The table below shows the relationship between ILEVEL settings and the IMASK values at which interrupts
are accepted.
Table 5.2.1 ILEVEL Settings and Accepted IMASK Values
ILEVEL values set
0 (ILEVEL = "000")
1 (ILEVEL = "001")
2 (ILEVEL = "010")
3 (ILEVEL = "011")
4 (ILEVEL = "100")
5 (ILEVEL = "101")
6 (ILEVEL = "110")
7 (ILEVEL = "111")
IREQ
Set
F/F
Set/clear
Interrupt enabled
Bits 5-7 or bits 13-15
ILEVEL
3
(levels 0-7)
Read
IREQ
b3, b11
Interrupt enabled
ILEVEL
b5-b7, b13-b15 3
(levels 0-7)
INTERRUPT CONTROLLER (ICU)
Reset
IVECT read
IMASK write
Interrupt priority
resolving circuit
Group interrupt
Read-only circuit
Reset
IVECT read
IMASK write
Interrupt priority
resolving circuit
IMASK values at which interrupts are accepted
Accepted when IMASK is 1–7
Accepted when IMASK is 2–7
Accepted when IMASK is 3–7
Accepted when IMASK is 4–7
Accepted when IMASK is 5–7
Accepted when IMASK is 6–7
Accepted when IMASK is 7
Not accepted (interrupts disabled)
5-10
5.2 ICU Related Registers
Clear
Set EI
To the CPU core
F/F
Clear
Set EI
To the CPU core
F/F
32180 Group User's Manual (Rev.1.0)