Renesas M32R/ECU Series User Manual page 493

12
12.1 Outline of Serial I/O
The 32180 contains a total of six serial I/O channels, SIO0–SIO5. Channels SIO0, SIO1, SIO4 and SIO5 can be
selected between CSIO mode (clock-synchronous serial I/O) and UART mode (clock-asynchronous serial I/O).
Channels SIO2 and SIO3 are UART mode only.
• CSIO mode (clock-synchronous serial I/O)
Communication is performed synchronously with a transfer clock, using the same clock on both transmit and
receive sides. The transfer data is 8 bits long (fixed).
• UART mode (clock-asynchronous serial I/O)
Communication is performed at any transfer rate in any transfer data format. The transfer data length can be
selected from 7, 8 and 9 bits.
Channels SIO0–SIO3 each have a transmit DMA transfer and a receive DMA transfer request. These serial
I/Os, when combined with the internal DMA Controller (DMAC), allow serial communication to be performed
at high speed, as well as reduce the data communication load of the CPU.
Serial I/O is outlined below.
Table 12.1.1 Outline of Serial I/O
Item
Number of channels
Clock
Transfer mode
BRG count source
(when internal clock selected)
Data format
Baud rate
Error detection
Fixed period clock output function
Note 1: The maximum input frequency of an external clock during CSIO mode is f(BCLK)/16.
Note 2: If f(BCLK) is selected as the count source, the BRG set value is subject to limitations.
Description
CSIO mode/UART mode : 4 channels (SIO0, SIO1, SIO4, SIO5)
UART only : 2 channels (SIO2, SIO3)
During CSIO mode : Internal clock or external clock as selected (Note 1)
During UART mode : Internal clock only
Transmit half-duplex, receive half-duplex, transmit/receive full-duplex
f(BCLK), f(BCLK)/8, f(BCLK)/32, f(BLCK)/256 (Note 2)
f(BCLK): Peripheral clock operating frequency
CSIO mode : Data length = 8 bits (fixed)
Order of transfer = LSB first (fixed)
UART mode : Start bit = 1 bit
Character length = 7, 8 or 9 bits
Parity bit = Added (odd, even) or not added
Stop bit = 1 or 2 bits
Order of transfer = LSB first (fixed)
CSIO mode : 152 bits/sec to 2 Mbits/sec (when f(BCLK) = 20 MHz)
UART mode : 19 bits/sec to 156 Kbits/sec (when f(BCLK) = 20 MHz)
CSIO mode : Overrun error only
UART mode : Overrun, parity and framing errors
(Occurrence of any of these errors is indicated by an error sum bit)
When using SIO0, SIO1, SIO4 and SIO5 as UART, this function outputs a divided-by-2
BRG clock from the SCLK pin.
12-2
Serial I/O
12.1 Outline of Serial I/O
32180 Group User's Manual (Rev.1.0)