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12
12.3.5 Processing at End of CSIO Transmission
When data transmission finishes, the following operation is automatically performed in hardware.
(1) When not transmitting successively
• The transmit status bit is cleared to "0".
(2) When transmitting successively
• When transmission of the last data in a consecutive data train finishes, the transmit status bit is cleared to "0".
12.3.6 Transmit Interrupts
(1) Transmit buffer empty interrupt
If the transmit buffer empty interrupt was selected using the SIO Interrupt Request Source Select Register, a
transmit buffer empty interrupt request is generated when data has been transferred from the transmit buffer
register to the transmit shift register. A transmit buffer empty interrupt request is also generated when the
TEN (Transmit Enable) bit is set to "1" (disabled → enabled) while the transmit buffer empty interrupt has
been enabled.
(2) Transmission finished interrupt
If the transmission finished interrupt was selected using the SIO Interrupt Request Source Select Register, a
transmission finished interrupt request is generated by a falling edge of the internal transfer clock pulse at
which the last bit of data in the transmit shift register has been transmitted or when the transmit enable bit is
cleared.
The SIO Interrupt Request Enable Register and the Interrupt Controller (ICU) must be set before these
transmit interrupts can be used.
12.3.7 Transmit DMA Transfer Request
When data has been transferred from the transmit buffer register to the transmit shift register, a transmit DMA
transfer request for the corresponding SIO channel is output to the DMAC. A transmit DMA transfer request is
also output when the TEN (Transmit Enable) bit is set to "1" (disabled → enabled).
The DMAC must be set before DMA transfers can be used during data transmission.
12.3 Transmit Operation in CSIO Mode
12-28
Serial I/O
32180 Group User's Manual (Rev.1.0)
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