Renesas M32R/ECU Series User Manual page 237

9
Table 9.3.10 DMA Transfer Request Sources and Generation Timings on DMA9
REQSL9 DMA Transfer Request Source
0 0 Software start
0 1 Serial I/O3 (transmit buffer empty) When serial I/O3 transmit buffer is empty
1 0 MJT (TIN8 input signal)
1 1 Extended DMA9 transfer request
source selected
REQESEL9 DMA Transfer Request Source
0000 One DMA8 transfer completed
0001 MJT (TOU0_7irq)
0010 A-D0 conversion completed
0011 MJT (input event bus 1)
0100 MJT (input event bus 3)
0101 MJT (output event bus 2)
0110 MJT (output event bus 3)
0111 A-D0 conversion completed
1000 MJT (TIN0 input signal)
1001 MJT (TIO8_udf)
1010
| Settings inhibited
1111
9.3 Functional Description of the DMAC
DMA Transfer Request Generation Timing
When any data is written to the DMA9 Software Request Generation Register
When MJT TIN8 input signal is generated
The source selected by the DMA9 Channel Control Register 1 (DM9CNT1)
REQESEL9 bits (see below)
DMA Transfer Request Generation Timing
When one DMA8 transfer is completed (cascade mode)
MJT TOU0_7 interrupt source
When A-D0 conversion is completed
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
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32180 Group User's Manual (Rev.1.0)
DMAC