Renesas M32R/ECU Series User Manual page 544

12
<UART on receive side>
Receive enable bit
SIO Receive Control Register)
Reception finished bit
Overrun error bit
SIO receive interrupt request
(Note 1)
(When reception finished
interrupt is selected)
(When receive error
interrupt is selected)
Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit
Note 2: When reception finished interrupt is enabled
Note 3: When receive error interrupt is enabled
Note 4: This is done by clearing the receive enable bit to "0".
Note 5: The Interrupt Controller's IVECT register is read or the SIO Receive Interrupt Control Register interrupt
request bit cleared
Figure 12.7.4 Example of UART Reception (When Overrun Error Occurred)
<UART on receive side>
RXD
Set
ST
RXD
Reception finished
interrupt request
: Processing by software
12.7 Receive Operation in UART Mode
<UART on transmit side>
TXD
First data reception
completed
b7 b7
SP ST
Receive buffer not read
during this interval
Set
(Note 2)
Interrupt request accepted (Note 5)
Receive error interrupt request
(Note 3)
Interrupt request accepted (Note 5)
: Interrupt request generated
12-53
SERIAL I/O
Next data reception
completed
SP
(Note 5)
Overrun error bit
cleared (Note 4)
32180 Group User's Manual (Rev.1.0)