Trap Processing; Trap - Renesas M32R/ECU Series User Manual

4
(6) Returning from the EIT handler
At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction.
When the RTE instruction is executed, hardware postprocessing is automatically performed.

4.10 Trap Processing

4.10.1 Trap

[Occurrence Conditions]
Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen traps are
generated, each corresponding to one of TRAP instruction operands 0–15. Accordingly, sixteen vector
entries are provided.
[EIT Processing]
(1) Saving SM, IE and C bits
The PSW register's SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC.
BSM ←
BIE
BC
(2) Updating SM, IE and C bits
The PSW register's SM, IE and C bits are updated as shown below.
SM
IE
C
(3) Saving the PC
When the trap instruction is executed, the PC value of TRAP instruction + 4 is set in the BPC register. For
example, if the TRAP instruction is located at address 4, the value H'08 is set in the BPC register.
Similarly, if the TRAP instruction is located at address 6, the value H'0A is set in the BPC register. The
value of the BPC register bit 30 indicates whether the trap instruction resides on a word boundary (BPC
register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1").
However, in either case of the above, the address to which the RTE instruction returns after the EIT
handler has terminated is address 8. (This is because the 2 low-order address bits are cleared to '00'
when returned to the PC.)
Address
H'00
H'04
Return
H'08
address
H'0C
Figure 4.10.1 Example of a Return Address for Trap (TRAP)
SM
←
IE
←
C
←
Unchanged
←
0
←
0
+0 +1 +2 +3
TRAP instruction
BPC H'08
Address
H'00
H'04
Return
H'08
address
H'0C
4-18
4.9 Interrupt Processing
+0 +1 +2 +3
TRAP instruction
BPC H'0A
32180 Group User's Manual (Rev.1.0)
EIT