Operation In Tou Pwm Output Mode - Renesas M32R/ECU Series User Manual

MULTIJUNCTION TIMERS
10
10.8 TOU (Output-Related 24-Bit Timer)

10.8.12 Operation in TOU PWM Output Mode

(1) Outline of TOU PWM output mode
In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle.
When the timer is enabled after setting the initial values in the reload 0 and reload 1 registers, the counter is
loaded with the reload 0 register value and starts counting down synchronously with the count clock. The first
time the counter underflows, it is loaded with the reload 1 register value and continues counting. Thereafter,
the counter is loaded with the reload 0 and reload 1 register values alternately each time an underflow
occurs. The (reload 0 register set value + 1) and (reload 1 register set value + 1) respectively are effective as
count values. The timer stops at the same time count is disabled by writing to the enable bit (and not in
synchronism with PWM output period).
The F/F output waveform in PWM output mode is inverted (F/F output level changes from "low" to "high" or
vice versa) when the counter starts counting and each time it underflows. An interrupt request can be gener-
ated when the counter underflows every other time (second time, fourth time and so on) after being enabled.
If the value 'FFFF' is set in the reload register, F/F output will not be inverted although an interrupt request is
generated upon underflow, making it possible to produce a 0% or 100% duty-cycle PWM output. Because a
0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count clock
equivalent delay before F/F is inverted and an interrupt or DMA transfer request is generated. However,
startup requests to other timers are not delayed. For details, see Section 10.8.17, "0% or 100% Duty-Cycle
Wave Output during PWM Output and Single-shot PWM Output Modes."
Note that TOU's PWM output mode does not have the count correction function.
32180 Group User's Manual (Rev.1.0)
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