Renesas M32R/ECU Series User Manual page 328

10
In the example below, the reload register is initially set to H'FFF8. When the timer starts, the reload register
value is loaded into the counter, letting it start counting down. In the diagram below, the value H'0014 is
written to the correction register when the counter has counted down to H'FFF0. As a result of this correction,
the count overflows to H'0004 and the counter fails to count correctly. Also, an interrupt request is generated
for an erroneous overflowed count.
correction register
Counter
Reload register
Correction register
TOP interrupt request
due to underflow
Figure 10.3.11 Example of an Operation in TOP Single-shot Output Mode Where Count Overflows Due to Correction
Enabled
(by writing to the enable bit
or by external input)
Count clock
Enable bit
Write to the
H'FFFF
H'FFF8
Undefined
value
H'0000
H'FFF8
Undefined
F/F output
Data inverted
by enable
Note: • This diagram does not show detailed timing information.
10.3 TOP (Output-Related 16-Bit Timer)
Disabled
(by underflow)
Overflow occurs
H'(FFF0+0014)
H'FFFF
H'(FFF8-1)
H'FFF0
H'0004
Actual count after overflow
H'0014
Data inverted
by underflow
10-85
MULTIJUNCTION TIMERS
32180 Group User's Manual (Rev.1.0)