Renesas M32R/ECU Series User Manual page 721

19
19.1 Outline of JTAG
The M32R/ECU contains a JTAG (Joint Test Action Group) interface compliant with IEEE Standard Test Access
Port and Boundary-Scan Architecture (IEEE Std. 1149.1a-1993). This JTAG interface can be used as an input/
output path for boundary-scan test (boundary-scan path). For details about IEEE 1149.1 JTAG test access ports,
see IEEE Std. 1149.1a-1993 documentation.
Note: • The JTAG interface in the M32R/ECU is used to connect a JTAG emulator during debugging as well.
In this chapter, the JTAG interface is explained assuming its use as an input/output path for boundary-scan
test.
Functions of the JTAG interface-related pins mounted on the M32R/ECU are shown below.
Table 19.1.1 JTAG Pin Functions
Type Pin Name Signal Name
TAP JTCK Test clock
(Note 1) JTDI Test data Input
JTDO Test data Output Output
JTMS Test mode select Input
JTRST Test reset
Note: TAP stands for Test Access Port (JTAG interface stipulated in IEEE 1149.1).
I/O Function
Input Clock input to the test circuit.
Input Synchronous serial data input pin used to supply the test instruction
code and test data. This input is sampled on the rising edge of JTCK.
Synchronous serial data output pin used to output the test instruction
code and test data. This signal changes state on the falling edge of JTCK,
and is output in only the Shift-IR or Shift-DR state. Otherwise, it goes to a
high-impedance state.
Test mode select input to control the test circuit's state transition. This input is
sampled on the rising edge of JTCK.
Input Active-low test reset input to initialize the test circuit asynchronously. To
ensure that the test circuit is reset without fail, JTMS input signal must be
held high while this signal changes state from low to high.
19-2
19.1 Outline of JTAG
32180 Group User's Manual (Rev.1.0)
JTAG