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16.1 Outline of the Wait Controller ----------------------------------------------------------------------------------------- 16-2
16.2 Wait Controller Related Registers ----------------------------------------------------------------------------------- 16-4
16.2.1
CS Area Wait Control Registers ---------------------------------------------------------------------------- 16-4
16.3 Typical Operation of the Wait Controller --------------------------------------------------------------------------- 16-6
17.1 Outline of RAM Backup Mode ---------------------------------------------------------------------------------------- 17-2
17.2 Example of RAM Backup when Power is Down ----------------------------------------------------------------------- 17-3
17.2.1
Normal Operating State --------------------------------------------------------------------------------------- 17-3
17.2.2
RAM Backup State --------------------------------------------------------------------------------------------- 17-4
17.3 Example of RAM Backup for Saving Power Consumption ---------------------------------------------------- 17-5
17.3.1
Normal Operating State --------------------------------------------------------------------------------------- 17-5
17.3.2
RAM Backup State --------------------------------------------------------------------------------------------- 17-6
17.3.3
Precautions to Be Observed at Power-On --------------------------------------------------------------- 17-7
17.4 Exiting RAM Backup Mode (Wakeup) ------------------------------------------------------------------------------ 17-8
18.1 Oscillator Circuit ---------------------------------------------------------------------------------------------------------- 18-2
18.1.1
Example of an Oscillator Circuit ---------------------------------------------------------------------------- 18-2
18.1.2
XIN Oscillation Stoppage Detection Circuit -------------------------------------------------------------- 18-3
18.1.3
Oscillation Drive Capability Select Function ------------------------------------------------------------- 18-5
18.1.4
System Clock Output Function ------------------------------------------------------------------------------ 18-7
18.1.5
Oscillation Stabilization Time at Power-On -------------------------------------------------------------- 18-7
18.2 Clock Generator Circuit ------------------------------------------------------------------------------------------------ 18-8
19.1 Outline of JTAG ---------------------------------------------------------------------------------------------------------- 19-2
19.2 Configuration of the JTAG Circuit ------------------------------------------------------------------------------------ 19-3
19.3 JTAG Registers ---------------------------------------------------------------------------------------------------------- 19-4
19.3.1
Instruction Register (JTAGIR) ------------------------------------------------------------------------------- 19-4
19.3.2
Data Register ---------------------------------------------------------------------------------------------------- 19-5
19.4 Basic Operation of JTAG ---------------------------------------------------------------------------------------------- 19-6
19.4.1
Outline of JTAG Operation ----------------------------------------------------------------------------------- 19-6
19.4.2
IR Path Sequence ---------------------------------------------------------------------------------------------- 19-8
19.4.3
DR Path Sequence -------------------------------------------------------------------------------------------- 19-9
19.4.4
Inspecting and Setting Data Registers -------------------------------------------------------------------- 19-10
19.5 Boundary Scan Description Language ----------------------------------------------------------------------------- 19-11
19.6 Notes on Board Design when Connecting JTAG ---------------------------------------------------------------------- 19-12
19.7 Processing Pins when Not Using JTAG ---------------------------------------------------------------------------- 19-14
20.1 Configuration of the Power Supply Circuit ------------------------------------------------------------------------- 20-2
20.2 Power-On Sequence ---------------------------------------------------------------------------------------------------- 20-3
20.2.1
Power-On Sequence when Not Using RAM Backup -------------------------------------------------- 20-3
20.2.2
Power-On Sequence when Using RAM Backup -------------------------------------------------------- 20-4
20.3 Power-Off Sequence ---------------------------------------------------------------------------------------------------- 20-5
20.3.1
Power-Off Sequence when Not Using RAM Backup -------------------------------------------------- 20-5
20.3.2
Power-Off Sequence when Using RAM Backup ------------------------------------------------------- 20-6
(9)
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