Renesas M32R/ECU Series User Manual page 489

11
(a) Example for calculating the external stabilizing capacitor C1 (addition of this capacitor is recommended)
Assuming the R1 in Figure 11.5.1 is infinitely large and that the current necessary to charge the internal
capacitor C2 is supplied from C1, if the potential fluctuation, Vp, caused by capacitance division of C1 and C2
is to be within 0.1 LSB, then what amount of capacitance C1 should have. For 10-bit A-D converters where
VREF is 5.12 V, 1 LSB determination voltage = 5.12 V / 1,024 = 5 mV. The potential fluctuation of 0.1 LSB
means a 0.5 mV fluctuation.
The relationship between the capacitance division of C1 and C2 and the potential fluctuation,
Vp, is obtained by the equation below:
Vp =
Vp is also obtained by the equation below:
Vp = Vp1 ×
When Eq. A-1 and Eq. A-2 are solved, the following results:
C1 = C2 {
∴
C1 > C2 {10 × 2
Thus, for 10-bit resolution A-D converters where C2 = 2.9 pF, C1 is 0.06 µF or more. Use this value for
reference when setting up C1.
(b) Maximum value of the output impedance R1 when C1 is not added
If the external capacitor C1 in Figure 11.5.1 is not used, examination must be made to see if the analog input
device can fully charge C2 within a predetermined time. First, the equation to find i2 when C1 in Figure 11.5.1
does not exist is shown below.
i2 =
Cin×R1+C2(R1+R2)
When sample-and-hold
is disabled
ADINi
Figure 11.5.2 A-D Conversion Timing Diagram
Figure 11.5.2 shows an A-D conversion timing diagram. C2 must be charged up within the sampling time
shown in this diagram. When the sample-and-hold function is disabled, the sampling time for the second and
subsequent bits is about half that of the first bit.
The sampling times at the respective conversion speeds are listed in the table 11.5.1. Note that when the
sample-and-hold function is enabled, the analog input is sampled for only the first bit.
C2
× (E - V2)
C1 + C2
x - 1
1 VREF
∑
<
i 10 × 2
2
i = 0
E - V2
- 1 }
Vp1
x - 1
1
×
× ∑
2
i = 0
C2(E - V2)
×exp
Conversion time
for the first bit
Sampling time Comparison
* When sample-and-hold is enabled, the analog input is sampled for only the first bit.
11.5 Precautions on Using A-D Converters
×
where Vp1 = potential fluctuation in the first A-D conversion performed
and x = 10 for a 10-bit resolution A-D converter
- 1 }
i
{ - t
Cin×R1+C2(R1+R2)
Second bit
Sampling time
time
Repeated (10 times) for 10 bits
11-44
A-D Converters
Eq. A-1
Eq. A-2
Eq. A-3
Eq. A-4
}
------------------------ Eq. B-1
32180 Group User's Manual (Rev.1.0)