Renesas M32R/ECU Series User Manual page 462

11
(2) ADSSEL (A-D Conversion Start Trigger Select) bit (Bit 3)
This bit selects whether to use a software or hardware trigger to start A-D conversion during single mode.
If a software trigger is selected, A-D conversion is started by setting the ADSSTT (A-D conversion start) bit to
"1". If a hardware trigger is selected, A-D conversion is started by the trigger source selected with the
ADSTRG (hardware trigger select) bits.
(3) ADSREQ (A-D Interrupt/DMA Transfer Request Select) bit (Bit 4)
This bit selects whether to request an A-D conversion interrupt or a DMA transfer when single mode opera-
tion (A-D conversion or comparate) is completed. If neither an interrupt nor a DMA transfer are used, choose
to request an A-D conversion interrupt and use the A-D Converter Interrupt Control Register of the Interrupt
Controller (ICU) to mask the interrupt request, or choose to request a DMA transfer and use the DMA Chan-
nel Control Register to disable DMA transfers to be performed upon completion of A-D conversion.
(4) ADSCMP (A-D Conversion/Comparate Completed) bit (Bit 5)
This is a read-only bit, whose value after reset is "1". This bit is "0" when the A-D Converter is performing
single mode operation (A-D conversion or comparate) and is set to "1" when the operation finishes.
This bit is also set to "1" when A-D conversion or comparate operation is forcibly terminated by setting the
ADSSTP (A-D conversion stop) bit to "1" during A-D conversion or comparate operation.
(5) ADSSTP (A-D Conversion Stop) bit (Bit 6)
Setting this bit to "1" while the A-D Converter is performing single mode operation (A-D conversion or
comparate) causes the operation being performed to stop. Manipulation of this bit is ignored while single
mode operation is idle or scan mode operation is under way.
Operation stops immediately after writing to this bit. If the A-D Successive Approximation Register is read
after being stopped, the content read from the register is the value in the middle of conversion (not trans-
ferred to the A-D Data Register).
If the A-D conversion start bit and A-D conversion stop bit are set to "1" at the same time, the A-D conversion
stop bit has priority.
If this bit is set to "1" when performing single mode operation in special mode "Forcible single mode execution
during scan mode," only single mode conversion stops and scan mode operation restarts.
(6) ADSSTT (A-D Conversion Start) bit (Bit 7)
If this bit is set to "1" when a software trigger has been selected with the ADSSEL (A-D conversion start
trigger select) bit, the A-D Converter starts A-D conversion.
If the A-D conversion start bit and A-D conversion stop bit are set to "1" at the same time, the A-D conversion
stop bit has priority.
If this bit is set to "1" again while performing single mode conversion, special operation mode "Conversion
restart" is turned on, so that single mode conversion restarts.
If this bit is set to "1" again while performing A-D conversion in scan mode, special operation mode "Forcible
single mode execution during scan mode" is turned on, so that the channel being converted in scan mode is
canceled and single mode conversion is performed. When the single mode conversion finishes, scan mode
A-D conversion restarts beginning with the canceled channel.
11.2 A-D Converter Related Registers
11-17
A-D Converters
32180 Group User's Manual (Rev.1.0)