Renesas M32R/ECU Series User Manual page 322

10
TOP Count Enable Register (TOPCEN)
b0 1 2
0 0 0
b Bit Name
0–4 No function assigned. Fix to "0".
5 TOP10CEN (TOP10 count enable bit)
6 TOP9CEN (TOP9 count enable bit)
7 TOP8CEN (TOP8 count enable bit)
8 TOP7CEN (TOP7 count enable bit)
9 TOP6CEN (TOP6 count enable bit)
10 TOP5CEN (TOP5 count enable bit)
11 TOP4CEN (TOP4 count enable bit)
12 TOP3CEN (TOP3 count enable bit)
13 TOP2CEN (TOP2 count enable bit)
14 TOP1CEN (TOP1 count enable bit)
15 TOP0CEN (TOP0 count enable bit)
Note: • This register must always be accessed in halfwords.
The TOP Count Enable Register controls operation of TOP counters. To enable any TOP counter in software,
enable its corresponding enable protect bit for write and set the count enable bit by writing "1". To stop any TOP
counter, enable its corresponding enable protect bit for write and reset the count enable bit by writing "0".
In all but continuous output mode, when the counter stops due to occurrence of an underflow, the count enable
bit is automatically reset to "0". Therefore, the TOP0-10 Count Enable Register when accessed for read serves
as a status register indicating whether the counter is operating or idle.
TINn
TOPm enable protect
Figure 10.3.6 Configuration of the TOP Enable Circuit
3 4 5 6
TOP10 TOP9
CEN CEN
0 0 0 0
TOPm external enable
(TOPmEEN)
F/F
Input processing
selection
TINnS
Event bus
(TOPmPRO)
F/F
WR
10.3 TOP (Output-Related 16-Bit Timer)
7 8 9 10
TOP8 TOP7 TOP6 TOP5
CEN CEN CEN CEN
0 0 0 0
Function
0: Stop counting
1: Enable counting
EN-ON
TOPm count enable
(TOPmCEN)
Dn
F/F
WR
10-79
MULTIJUNCTION TIMERS
<Address: H'0080 02FE>
11 12 13 14
TOP4 TOP3 TOP2 TOP1
CEN CEN CEN CEN
0 0 0 0
<After reset: H'0000>
TOP enable control
32180 Group User's Manual (Rev.1.0)
b15
TOP0
CEN
0
R W
0 0
R W