Sio Transmit/Receive Mode Registers - Renesas M32R/ECU Series User Manual

12

12.2.3 SIO Transmit/Receive Mode Registers

SIO0 Transmit/Receive Mode Register (S0MOD)
SIO1 Transmit/Receive Mode Register (S1MOD)
SIO2 Transmit/Receive Mode Register (S2MOD)
SIO3 Transmit/Receive Mode Register (S3MOD)
SIO4 Transmit/Receive Mode Register (S4MOD)
SIO5 Transmit/Receive Mode Register (S5MOD)
b8 9 10
SMOD
0 0 0
b Bit Name
8–10 SMOD
Serial I/O mode select bit
(Note 1)
11 CKS
Internal/external clock select bit
12 STB
Stop bit length select bit, UART mode only
13 PSEL
Odd/even parity select bit, UART mode only
14 PEN
Parity enable bit, UART mode only
15 SEN
Sleep select bit, UART mode only
Note 1: For SIO2 and 3, bit 8 is fixed to "0" in hardware. This bit cannot be set to "1" in software (to select clock-synchronous serial I/O).
Note 2: Has no effect when UART mode selected.
Note 3: Bits 12–15 have no effect during clock-synchronous mode.
The SIO Mode Registers consist of bits to set the serial I/O operation mode, data format and the functions used
during communication.
The SIO Transmit/Receive Mode Registers must always be set before the serial I/O starts operating. To change
register settings before the serial I/O starts sending or receiving data, first confirm that transmit and receive
operations have finished and then disable transmit/receive operations (by clearing the SIO Transmit Control
Register transmit enable bit and SIO Receive Control Register receive enable bit to "0") before making changes.
(1) SMOD (Serial I/O Mode Select) bits (Bits 8–10)
These bits select the operation mode of serial I/O.
(2) CKS (Internal/External Clock Select) bit (Bit 11)
This bit is effective when CSIO mode is selected. Setting this bit has no effect when UART mode is selected,
in which case the serial I/O is clocked by the internal clock.
(3) STB (Stop Bit Length Select) bit (Bit 12)
This bit is effective during UART mode. Use this bit to select the stop bit length that indicates the end of data
to transmit. Setting this bit to "0" selects one stop bit, and setting this bit to "1" selects two stop bits.
During clock-synchronous mode, the content of this bit has no effect.
11 12 13 14
CKS STB PSEL PEN
0 0 0 0
12.2 Serial I/O Related Registers
b15
SEN
0
Function
b8 b9 b10
0 0 0 : 7-bit UART
0 0 1 : 8-bit UART
0 1 X : 9-bit UART
1 X X : 8-bit clock-synchronous serial I/O
0: Internal clock
1: External clock
0: One stop bit
1: Two stop bits
0: Odd parity
1: Even parity
0: Disable parity
1: Enable parity
0: Disable sleep function
1: Enable sleep function
12-15
Serial I/O
<Address: H'0080 0111>
<Address: H'0080 0121>
<Address: H'0080 0131>
<Address: H'0080 0141>
<Address: H'0080 0A11>
<Address: H'0080 0A21>
<After reset: H'00>
R
R
R
R
R
R
R
32180 Group User's Manual (Rev.1.0)
W
W
W
(Note 2)
W
(Note 3)
W
(Note 3)
W
(Note 3)
W
(Note 3)