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21
(8) JTAG interface timing
Symbol
tc(JTCK)
JTCK Input Cycle Time
tw(JTCKH)
JTCK Input High Pulse Width
tw(JTCKL)
JTCK Input Low Pulse Width
tsu(JTDI-JTCK)
JTDI, JTMS Input Setup Time
th(JTCK-JTDI)
JTDI, JTMS Input Hold Time
td(JTCK-JTDOV)
JTDO Output Delay Time after JTCK Fall
td(JTCK-JTDOX)
JTDO Output Hi-Z Delay Time after JTCK Fall
tw(JTRST)
JTRST Input Low Pulse Width
Note: • The rated values here are guaranteed for the case where the measured pin load capacitance CL = 80 pF.
(9) RTD timing
Symbol
tc(RTDCLK)
tw(RTDCLKH)
tw(RTDCLKL)
td(RTDCLKH-RTDACK)
tv(RTDCLKL-RTDACK)
td(RTDCLKH-RTDTXD)
th(RTDCLKH-RTDRXD)
tsu(RTDRXD-RTDCLKL) RTDRXD Input Setup Time
Parameter
Parameter
RTDCLK Input Cycle Time
RTDCLK Input High Pulse Width
RTDCLK Input Low Pulse Width
RTDACK Delay Time after RTDCLK Input
RTDACK Valid Time after RTDCLK Input
RTDTXD Delay Time after RTDCLK Input
RTDRXD Input Hold Time
ELECTRICAL CHARACTERISTICS
21.7 A.C. Characteristics (when VCCE = 5 V)
Rated Value
MIN
100
40
40
15
20
tc(JTCK)
Rated Value
MIN
500
230
230
50
60
21-23
Unit
MAX
ns
ns
ns
ns
ns
40
ns
40
ns
ns
Unit
MAX
ns
ns
ns
160
ns
160
ns
160
ns
ns
tc(RTDCLK)
ns
+160
2
32180 Group User's Manual (Rev.1.0)
See Fig.
21.7.13
[60]
[61]
[62]
[63]
[64]
[65]
[66]
[67]
See Fig.
21.7.14
[82]
[83]
[84]
[85]
[86]
[87]
[88]
[89]
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