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M16C/29 Group
7.7 System Clock Protective Function
When the main clock is selected for the CPU clock source, this function protects the clock from modifica-
tions in order to prevent the CPU clock from becoming halted by run-away.
If the PM21 bit of PM2 register is set to "1" (clock modification disabled), the following bits are protected
against writes:
• CM02, CM05, and CM07 bits in CM0 register
• CM10, CM11 bits in CM1 register
• CM20 bit in CM2 register
• All bits in PLC0 register
Before the system clock protective function can be used, the following register settings must be made while
the CM05 bit of CM0 register is "0" (main clock oscillating) and CM07 bit is "0" (main clock selected for the
CPU clock source):
(1) Set the PRC1 bit of PRCR register to "1" (enable writes to PM2 register).
(2) Set the PM21 bit of PM2 register to "1" (disable clock modification).
(3) Set the PRC1 bit of PRCR register to "0" (disable writes to PM2 register).
Do not execute the WAIT instruction when the PM21 bit is "1".
7.8 Oscillation Stop and Re-oscillation Detect Function
The oscillation stop and re-oscillation detect function allows the detection of main clock oscillation stop and
reoscillation. At oscillation stop or re-oscillation detection, depending on the setting of the CM27 setting,
either a reset or an interrupt (oscillation stop or re-oscillation detect) will be generated. Depending on the
CM27 bit of CM2 register. The oscillation stop detection function can be enabled and disabled by the CM20
bit in the CM2 register. Table 7.8.1 lists a specification overview of the oscillation stop and re-oscillation
detect function.
Table 7.8.1. Specification Overview of Oscillation Stop and Re-oscillation Detect Function
Item
Oscillation stop detectable clock and
frequency bandwidth
Enabling condition for oscillation stop,
re-oscillation detection function
Operation at oscillation stop,
re-oscillation detection
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
f(X
Set CM20 bit to "1"(enable)
•Reset occurs (when CM27 bit =0)
•Oscillation stop, re-oscillation detection interrupt occurs(when CM27 bit =1)
page 57 of 402
Specification
) ≥ 2 MHz
IN
7. Clock Generation Circuit
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