Renesas M32R/ECU Series User Manual page 236

9
Table 9.3.8 DMA Transfer Request Sources and Generation Timings on DMA7
REQSL7 DMA Transfer Request Source
0 0 Software start
0 1 Serial I/O2 (transmit buffer empty) When serial I/O2 transmit buffer is empty
1 0 MJT (TIN2 input signal)
1 1 Extended DMA7 transfer request
source selected
REQESEL7 DMA Transfer Request Source
0000 One DMA6 transfer completed
0001 MJT (TOU0_2irq)
0010 Serial I/O3 (reception completed) When serial I/O3 reception is completed
0011 MJT (input event bus 1)
0100 MJT (input event bus 3)
0101 MJT (output event bus 2)
0110 MJT (output event bus 3)
0111 A-D0 conversion completed
1000 MJT (TIN0 input signal)
1001 MJT (TIO8_udf)
1010
| Settings inhibited
1111
Table 9.3.9 DMA Transfer Request Sources and Generation Timings on DMA8
REQSL8 DMA Transfer Request Source
0 0 Software start
0 1 MJT (input event bus 0)
1 0 Serial I/O3 (reception completed) When serial I/O3 reception is completed
1 1 Extended DMA8 transfer request
source selected
REQESEL8 DMA Transfer Request Source
0000 MJT (TIN7 input signal)
0001 MJT (TOU0_6irq)
0010 One DMA7 transfer completed
0011 MJT (input event bus 1)
0100 MJT (input event bus 3)
0101 MJT (output event bus 2)
0110 MJT (output event bus 3)
0111 A-D0 conversion completed
1000 MJT (TIN0 input signal)
1001 MJT (TIO8_udf)
1010
| Settings inhibited
1111
9.3 Functional Description of the DMAC
DMA Transfer Request Generation Timing
When any data is written to the DMA7 Software Request Generation Register
When MJT TIN2 input signal is generated
The source selected by the DMA7 Channel Control Register 1 (DM7CNT1)
REQESEL7 bits (see below)
DMA Transfer Request Generation Timing
When one DMA6 transfer is completed (cascade mode)
MJT TOU0_2 interrupt source
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
–
DMA Transfer Request Generation Timing
When any data is written to the DMA8 Software Request Generation Register
When MJT input event bus 0 signal is generated
The source selected by the DMA8 Channel Control Register 1 (DM8CNT1)
REQESEL8 bits (see below)
DMA Transfer Request Generation Timing
When MJT TIN7 input signal is generated
MJT TOU0_6 interrupt source
When one DMA7 transfer is completed (cascade mode)
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
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32180 Group User's Manual (Rev.1.0)
DMAC