Renesas M32R/ECU Series User Manual page 800

Appendix 2
The following shows the number of memory access cycles in the IF and MEM stages. Shown here are the mini-
mum number of cycles required for memory access. Therefore, these values do not always reflect the number of
cycles actually required for memory or bus access.
In write access, for example, although the CPU finishes the MEM stage by only writing to the write buffer, this
operation actually is followed by a write to memory. Depending on the memory or bus state before or after the CPU
requests a memory access, the instruction processing may take more time than the calculated value.
• Read (read cycle)
When existing in the instruction queue ..................................................... 1 CPUCLK cycle
When reading the internal resource (RAM) .............................................. 1 CPUCLK cycle
When reading the internal resource (ROM) .............................................. 2 CPUCLK cycles
When reading the internal resource (SFR) (byte or halfword) .................. 4 CPUCLK cycles
When reading the internal resource (SFR) (word) .................................... 8 CPUCLK cycles
When reading external memory (byte or halfword) ................................... 1 CPUCLK + 1 BCLK cycles (Note 1)
When reading external memory (word) .................................................... 1 CPUCLK + 2 BCLK cycles (Note 1)
When successively fetching instructions from external memory .............. 2 BCLK cycles (Note 1)
• W (write cycle)
When writing to the internal resource (RAM) ........................................... 1 CPUCLK cycle
When writing to the internal resource (SFR) (byte or halfword) ................ 4 CPUCLK cycles
When writing to the internal resource (SFR) (word) ................................. 8 CPUCLK cycles
When writing to external memory (byte or halfword) ................................ 1 BCLK cycle (Note 1)
When writing to external memory (word) .................................................. 2 BCLK cycles (Note 1)
Note 1: This applies when external memory is accessed with zero wait state. The instruction processing
time increases by 1 BCLK when one wait state is inserted.
Note: • BCLK and CPUCLK have the relationship 1 BCLK = 4 CPUCLK.
INSTRUCTION PROCESSING TIME
Appendix 2.1 32180 Instruction Processing Time
Appendix 2-3
32180 Group User's Manual (Rev. 1.0)