Renesas M32R/ECU Series User Manual page 43

2
26 CU
Underflow Exception Cause Bit
27 CZ
Zero Divide Exception Cause Bit
28 CO
Overflow Exception Cause Bit
29 CV
Invalid Operation Exception Cause Bit 1: An invalid operation exception occurred. When the bit is set to "1",
30, 31 RM
Rounding Mode Selection Bit
Note 1: The phrase "If EIT processing unexecuted" means whenever one of the exceptions occurs, enable bits 17 to 21 are set to
"0" which masks the EIT processing so that it cannot be executed. If two exceptions occur at the same time and their
corresponding exception enable bits are set differently (one enabled, and the other masked), EIT processing is executed. In
this case, these two flags do not change state regardless of the enable bits settings.
Note 2: If a denormalized number is given to the operand when DN = "0", an unimplemented exception occurs.
Note 3: This bit is cleared by writing "0". Writing "1" has no effect (the bit retains the value it had before the write).
0: No underflow exception occurred
1: An underflow exception occurred. When the bit is set to "1",
the execution of an FPU operation instruction will clear it to "0".
0: No zero divide exception occurred.
1: A zero divide exception occurred. When the bit is set to "1",
the execution of an FPU operation instruction will clear it to "0".
0: No overflow exception occurred.
1: An overflow exception occurred. When the bit is set to "1",
the execution of an FPU operation instruction will clear it to "0".
0: No invalid operation exception occurred.
the execution of an FPU operation instruction will clear it to "0".
00: Round to nearest
01: Round toward Zero
10: Round toward + Infinity
11: Round toward – Infinity
2-6
2.3 Control Registers
R
R
R
R
R
32180 Group User's Manual (Rev.1.0)
CPU
(Note 3)
(Note 3)
(Note 3)
(Note 3)
W