Example Of Csio Receive Operation - Renesas M32R/ECU Series User Manual

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12.4.6 Example of CSIO Receive Operation

The following shows a typical receive operation in CSIO mode.
<CSIO on receive side>
Receive clock
(SCLKO)
Receive enable bit
RXD
Receive status bit
Reception finished bit
SIO receive interrupt request
(Note 1)
(When reception finished
interrupt is selected)
(When receive error
interrupt is selected)
Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit
Note 2: When reception finished interrupt is enabled (DMA transfer can also be requested at the same time)
Note 3: The Interrupt Controller's IVECT register is read or the SIO Receive Interrupt Control Register
interrupt request bit cleared
Figure 12.4.3 Example of CSIO Reception (When Received Normally)
<CSIO on receive side>
SCLKO
RXD
Internal clock selected
Set
b7
Set by a write to
the transmit buffer
No interrupt request
: Processing by software
12.4 Receive Operation in CSIO Mode
<CSIO on transmit side>
SCLKI
TXD
External clock selected
b6 b5 b4 b3 b2
Reception finished interrupt request
(Note 2)
Interrupt request accepted (Note 3)
: Interrupt request generated
12-37
Serial I/O
Clock stops
Cleared
b1 b0
Automatically cleared for each
receive operation performed
Read from the
receive buffer
32180 Group User's Manual (Rev.1.0)