Renesas M32R/ECU Series User Manual page 686

16
Bus Mode Control Register (Note 1)
BUSMOD bit = 0 (WR signal separated)
CS Area Wait Control Register (Note 2)
WTCSEL bit = 111 (7 wait)
SWAIT bit = 0 (without strobe wait)
RECOV bit = 0 (without recovery cycle)
IDLE bit = 0 (without idle cycle)
Read
BCLK
A11–A30
CS0#–CS3#
RD#
BHW#, BLW#
DB0–DB15
WAIT#
Write
BCLK
A11–A30
CS0#–CS3#
RD#
BHW#, BLW#
DB0–DB15
WAIT#
Note 1: For details about the Bus Mode Control Register, see Section 15.2.3, "Bus Mode Control Register."
Note 2: For details about the CS Area Wait Control Register, see Section 16.2.1, "CS Area Wait Control Registers."
Note: • Circles in the above diagram indicate the sampling timing.
Figure 16.3.4 Read/Write Timing (for Access with Internal 7 Wait States)
"H"
(Don't Care)
"H"
(Don't Care)
16-9
16.3 Typical Operation of the Wait Controller
Read (8 cycles)
Internal 7 wait states
Write (8 cycles)
Internal 7 wait states
32180 Group User's Manual (Rev.1.0)
WAIT CONTROLLER
(Don't Care)
"H"
(Don't Care)
"H"