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12
12.4.2 Starting CSIO Reception
The serial I/O starts receive operation when all of the following conditions are met after being initialized.
(1) Receive conditions when CSIO mode internal clock is selected
• The SIO Receive Control Register receive enable bit is set to "1".
• Transmit conditions are met. (See Section 12.3.3, "Starting CSIO Transmission.")
(2) Receive conditions when CSIO mode external clock is selected
• The SIO Receive Control Register receive enable bit is set to "1".
• Transmit conditions are met. (See Section 12.3.3, "Starting CSIO Transmission.")
Note: • The receive status bit is set to "1" at the time dummy data is set in the lower byte of the SIO
Transmit Buffer Register.
When the above conditions are met, the serial I/O starts receiving 8-bit serial data (LSB first) synchronously with
the receive shift clock.
12.4.3 Processing at End of CSIO Reception
When data reception finishes, the following operation is automatically performed in hardware.
(1) When reception is completed normally
The reception finished (receive buffer full) bit is set to "1".
Notes: • An interrupt request is generated if the reception finished (receive buffer full) interrupt has been enabled.
• A DMA transfer request is generated.
(2) When an error occurred during reception
If an error (only overrun error in CSIO mode) occurred during reception, the overrun error bit and receive
error sum bit are set to "1".
Notes: • If the reception finished interrupt has been selected (by SIO Receive Interrupt Request Source Select
Register), neither a reception finished interrupt request nor a DMA transfer request is generated.
• If the receive error interrupt has been selected (by SIO Receive Interrupt Request Source
Select Register), a receive error interrupt request is generated when interrupt requests are
enabled. No DMA transfer requests are generated.
12.4 Receive Operation in CSIO Mode
12-34
Serial I/O
32180 Group User's Manual (Rev.1.0)
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