STMicroelectronics STM32F405 Reference Manual page 712

Cryptographic processor (CRYP)
Table 111. Number of cycles required to process each 128-bit block
192b 16
256b 18
•
DES/TDES
–
–
–
–
–
–
•
Common to DES/TDES and AES
–
–
–
712/1731
16 16 28
18 18 32
Direct implementation of simple DES algorithms (a single key, K1, is used)
Supports the ECB and CBC chaining algorithms
Supports 64-, 128- and 192-bit keys (including parity)
2 × 32-bit initialization vectors (IV) used in the CBC mode
16 HCLK cycles to process one 64-bit block in DES
48 HCLK cycles to process one 64-bit block in TDES
IN and OUT FIFO (each with an 8-word depth, a 32-bit width, corresponding to 4
DES blocks or 2 AES blocks)
Automatic data flow control with support of direct memory access (DMA) (using 2
channels, one for incoming data the other for processed data)
Data swapping logic to support 1-, 8-, 16- or 32-bit data
DocID018909 Rev 11
(STM32F43xxx)
10 16
10 18
16 14 16
18 16 18
RM0090
29 16
33 18