Bus Switch, Bus Switch Priorities - Infineon Technologies TC1728 User Manual

TC1728
Direct Memory Access Controller (DMA)
DMA Channels 0n of Sub-Block m
DMA DMA DMA DMA DMA DMA DMA DMA
CH CH CH CH CH CH CH CH
00 01 02 03 04 05 06 07
DMA Channel Arbiter
Move Engine m
Transaction Control Unit m
Bus Switch
MCA06161
Figure 11-13 Transaction Control Engine (m = 0-1)
11.2.6

Bus Switch, Bus Switch Priorities

The Bus Switch of the DMA controller provides the connection from the DMA Sub-Blocks
to the two On Chip Bus master interfaces (connected to System Peripheral Bus and LMB
Bus) and to the DMA Peripheral Interface (see Figure 11-14).
The FPI Bus interface of the DMA includes a slave interface which provides the access
to the DMA and the peripherals connected to the DMA Peripheral Interface (MLI,
Cerberus and Memory Checker modules).
The LMB Bus interface of the DMA is a master interface.
The DMA module, the DMA Sub-Blocks as well as the MLI, the Memory Checker and the
Cerberus module working frequencies are identical to the FPI Bus frequency. The
working frequency of the LMB master interface is identical to the LMB/CPU working
frequency.
User's Manual 11-22 2011-12
DMA, V1.0