Slave Select Output Generation Unit - Infineon Technologies TC1728 User Manual

– MRST is driven with the logic level of bit PISEL.STIP (slave transmit idle state).
– SCLKI is driven with the logic level of CON.PO (clock polarity control).
• SLSI = 0: SSC is selected as slave.
– The slave receive input signals MTSRA or MTSRB are connected to MTSRI,
depending on PISEL.SRIS (Slave Mode receive input select).
– MRST is directly driven with the slave transmit output signal MRSTI.
– The slave clock input signals SCLKA or SCLKB are connected to SCLKI,
depending on PISEL.SCIS (Slave Mode clock input select).

18.1.2.9 Slave Select Output Generation Unit

In Master Mode, the slave select output generation unit of the SSC automatically
generates up to eight slave select output lines SLSO[7:0] for serial transmit operations.
The slave select output generation unit further makes it possible to adjust the chip select
timing parameters. The active/inactive state of a slave select output as well as the
enable/disable state can be controlled individually for each slave select output (see
Figure 18-10). The basic slave select output timing is shown in
a low active level of the SLSOn lines.
SCLK
Sample points
MRST
SLSOn
MTSR Invalid
Note: This timing example is based on the following setup: CON.PH = 0; CON.PO = 1
Figure 18-9 SSC Slave Select Output Timing
A slave select output period always starts after a write operation to register TB. With a
TB write operation, all timing parameters stored in register SSOTC (LEAD, TRAIL,
User's Manual
SSC, V1.41 2010-06
t
SCLK
First
Bit
t
SLSOL
t
SLSOACT
First
Bit
Data Frame
Slave Select Output Period
18-17
Synchronous Serial Interface (SSC)
Figure
Last
Bit
t
SLSOI
t
SLSOT
Last
Invalid
Bit
TC1728
18-9, assuming
First
Bit
t
SLSOL
First
Bit
MCT06220_mod
V1.0, 2011-12